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M48Z2M1Y M48Z2M1V
5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER(R) SRAM
Features

Integrated, ultra low power SRAM, power-fail control circuit, and batteries Conventional SRAM operation; unlimited WRITE cycles 10 years of data retention in the absence of power Automatic power-fail chip deselect and WRITE protection WRITE protect voltages (VPFD = Power-fail deselect voltage): - M48Z2M1Y: VCC = 4.5 to 5.5 V 4.2 V VPFD 4.5 V - M48Z2M1V: VCC = 3.0 to 3.6 V 2.8 V VPFD 3.0 V M48Z2M1V not recommended for new design. Contact ST sales office for availability. Batteries are internally isolated until power is applied Pin and function compatible with JEDEC standard 2 Mb x 8 SRAMs RoHS compliant - Lead-free second level interconnect
36 1
PLDIP36 module (PL)

August 2010
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www.st.com 1
Contents
M48Z2M1Y, M48Z2M1V
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLDIP36 - 36-pin plastic DIP long module, package mechanical data . . . . . . . . . . . . . . . 16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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List of figures
M48Z2M1Y, M48Z2M1V
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8 WRITE enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLDIP36 - 36-pin plastic DIP long module, package outline . . . . . . . . . . . . . . . . . . . . . . . 16 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Description
1
Description
The M48Z2M1Y/V ZEROPOWER(R) RAM is a non-volatile 16,777,216-bit, static RAM organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries, CMOS SRAMs and a control circuit in a plastic 36-pin DIP, long module. The ZEROPOWER RAM replaces industry standard SRAMs. It provides the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Figure 1. Logic diagram
VCC
21 A0-A20 M48Z2M1Y M48Z2M1V
8 DQ0-DQ7
W E G
VSS
AI02048
Table 1.
Signal names
A0-A20 Address inputs Data inputs / outputs Chip enable Output enable WRITE enable Supply voltage Ground Not connected internally
DQ0-DQ7 E G W VCC VSS NC
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Description Figure 2. DIP connections
NC A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 36 2 35 34 3 33 4 5 32 6 31 30 7 29 8 M48Z2M1Y 9 M48Z2M1V 28 27 10 26 11 25 12 24 13 14 23 15 22 16 21 20 17 19 18 VCC A19 NC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
M48Z2M1Y, M48Z2M1V
AI02049
Figure 3.
Block diagram
VCC A0-A20
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
2048K x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERIES
VSS
AI02050
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Operation modes
2
Operation modes
The M48Z2M1Y/V has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operations brought on by low VCC. As VCC falls below approximately 3 V, the control circuitry connects the batteries which sustain data until valid power returns. Table 2.
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD VSO (min)(1)
(1)
Operating modes
VCC E VIH 3.0 to 3.6 V or 4.5 to 5.5 V VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery backup mode
1. See Table 10 on page 15 for details.
Note:
X = VIH or VIL; VSO = battery backup switchover voltage.
2.1
READ mode
The M48Z2M1Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of 16,777,216 locations in the static storage array. Thus, the unique address specified by the 21 address inputs defines which one of the 2,097,152 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E (chip enable) and G (output enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of chip enable access time (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain low, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access. Figure 4. Address controlled, READ mode AC waveforms
A0-A20 tAVAV tAVQV DQ0-DQ7 DATA VALID AI02051 tAXQX
Note:
Chip enable (E) and output enable (G) = low, WRITE enable (W) = high.
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Operation modes Figure 5.
M48Z2M1Y, M48Z2M1V Chip enable or output enable controlled, READ mode AC waveforms
tAVAV A0-A20 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT AI02052 tGHQZ VALID tAXQX tEHQZ
Note:
WRITE enable (W) = high. Table 3. READ mode AC characteristics
M48Z2M1Y Symbol Parameter(1) Min tAVAV tAVQV(2) tAXQX(2) tEHQZ
(3)
M48Z2M1V -85 Unit Max ns 85 5 ns ns 35 85 5 ns ns ns 35 45 5 ns ns ns
-70 Max Min 85 70 5 30 70 5 25 35 5
READ cycle time Address valid to output valid Address transition to output transition Chip enable high to output Hi-Z Chip enable low to output valid Chip enable low to output transition Output enable high to output Hi-Z Output enable low to output valid Output enable low to output transition
70
tELQV(2) tELQX(3) tGHQZ(3) tGLQV(2) tGLQX(3)
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 100 pF or 50 pF (see Figure 9 on page 13). 3. CL = 5 pF (see Figure 9 on page 13).
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Operation modes
2.2
WRITE mode
The M48Z2M1Y/V is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 6. WRITE enable controlled, WRITE mode AC waveforms
tAVAV A0-A20 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH AI02053 tWHQX tWHAX
Note:
Output enable (G) = high. Figure 7. Chip enable controlled, WRITE mode AC waveforms
tAVAV A0-A20 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI02054 tELEH tEHAX
Note:
Output enable (G) = high.
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Operation modes Table 4. WRITE mode AC characteristics
M48Z2M1Y, M48Z2M1V
M48Z2M1Y Symbol Parameter(1) Min tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tWHAX tWHDX tWHQX(2)(3) tWLQZ(2)(3) tWLWH WRITE cycle time Address valid to chip enable high Address valid to chip enable low Address valid to WRITE enable high Address valid to WRITE enable low Input valid to chip enable high Input valid to WRITE enable high Chip enable high to address transition Chip enable high to input transition Chip enable low to chip enable high WRITE enable high to address transition WRITE enable high to input transition WRITE enable high to output transition WRITE enable low to output Hi-Z WRITE enable pulse width 55 70 65 0 65 0 30 30 15 10 55 5 0 5 25 -70 Max
M48Z2M1V -85 Min 85 75 0 75 0 35 35 15 15 75 5 0 5 30 65 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6V (except where noted). 2. CL = 5 pF (see Figure 9 on page 13). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z2M1Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "Don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cells will maintain data in the M48Z2M1Y/V after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the batteries are disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on battery storage life refer to the application note AN1012.
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Operation modes
2.4
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 F (as shown in Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 8. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS AI02169
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Maximum ratings
M48Z2M1Y, M48Z2M1V
3
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
Symbol TA TSTG TBIAS TSLD(1) VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature (VCC off) Temperature under bias Lead solder temperature for 10 seconds Input or output voltages Supply voltage Output current Power dissipation M48Z2M1Y M48Z2M1V M48Z2M1Y M48Z2M1V Value 0 to 70 -40 to 85 -40 to 85 260 -0.3 to 7 -0.3 to 4.6 -0.3 to 7 -0.3 to 4.6 20 1 Unit C C C C V V V V mA W
1. Soldering temperature of the IC leads is to not exceed 260 C for 10 seconds. In order to protect the lithium battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 C. Furthermore, the devices shall not be exposed to IR reflow.
Caution:
Negative undershoots below -0.3 V are not allowed on any pin while in the battery backup mode.
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DC and AC parameters
4
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M48Z2M1Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 M48Z2M1V 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pF ns V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC testing load circuit
5V
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF (Y) 50pF or 5pF (V)
CL includes JIG capacitance
AI07816
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DC and AC parameters Table 7.
Symbol CIN CIO
(3)
M48Z2M1Y, M48Z2M1V
Capacitance
Parameter(1)(2) Input capacitance Input / output capacitance Min Max 40 40 Unit pF pF
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. Outputs deselected. 3. At 25 C.
Table 8.
Sym ILI(2) ILO
(2)
DC characteristics
Parameter Test condition(1) 0 V VIN VCC 0 V VOUT VCC E = VIL, Outputs open E = VIH E VCC - 0.2 V -0.3 2.2 IOL = 2.1 mA IOH = -1 mA 2.4 M48Z2M1Y Min Max 4 4 140 10 8 0.8 VCC + 0.3 0.4 2.2 -0.3 2.2 M48Z2M1V Unit Min Max 4 4 70 2 1 0.6 VCC + 0.3 0.4 A A mA mA mA V V V V
Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output high voltage
ICC ICC1 ICC2 VIL VIH VOL VOH
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. Outputs deselected.
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M48Z2M1Y, M48Z2M1V Figure 10. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWP E
RECOGNIZED
DC and AC parameters
tDR tRB
tR
tER DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
Table 9.
Symbol tER tF(2) tFB(3) tR tWP
Power down/up AC characteristics
Parameter(1) E recovery time VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSO VCC fall time VPFD (min) to VPFD (max) VCC rise time Write protect time from VCC = VPFD M48Z2M1Y M48Z2M1V M48Z2M1Y M48Z2M1V Min 40 300 10 150 10 40 40 150 250 Max 120 Unit ms s s s s s s
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Symbol VPFD VSO tDR
(3)
Power down/up trip points DC characteristics
Parameter(1)(2) Power-fail deselect voltage M48Z2M1Y M48Z2M1V M48Z2M1Y M48Z2M1V 10 Min 4.2 2.8 Typ 4.3 2.9 3.0 2.45 Max 4.5 3.0 Unit V V V V YEARS
Battery backup switchover voltage Expected data retention time
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 3. At 25 C; VCC = 0 V.
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Package mechanical data
M48Z2M1Y, M48Z2M1V
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 11. PLDIP36 - 36-pin plastic DIP long module, package outline
A
A1 S B e3 D e1
L eA
C
N
E
1
PMDIP
Note:
Drawing is not to scale. Table 11.
Symb Typ A A1 B C D E e1 e3 eA L S N 43.18 14.99 3.05 4.45 36 16.00 3.81 5.33 Min 9.27 0.38 0.43 0.20 52.58 18.03 2.30 0.59 0.33 53.34 18.80 2.81 1.7 0.5902 0.1201 0.1752 36 0.6299 0.1500 0.2098 Max 9.52 Typ Min 0.3650 0.0150 0.0169 0.0079 2.0701 0.7098 0.0906 0.0232 0.0130 2.1000 0.7402 0.1106 Max 0.3748
PLDIP36 - 36-pin plastic DIP long module, package mechanical data
mm inches
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Part numbering
6
Part numbering
Table 12.
Example:
Ordering information scheme
M48Z 2M1Y -70 PL 1
Device type M48Z
Supply voltage and write protect voltage 2M1Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V 2M1V = VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V(1)
Speed -70 = 70 ns (Y) -85 = 85 ns (V)(1)
Package PL = PLDIP36
Temperature range 1 = 0 to 70C 9(2) = extended temperature
Shipping method blank = ECOPACK(R) package, tubes
1. Not recommended for new design. Contact ST sales office for availability. 2. Contact ST sales office for availability of extended temperature.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Environmental information
M48Z2M1Y, M48Z2M1V
7
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Please refer to the following web site address for additional information regarding compliance statements and waste recycling. Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
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Revision history
8
Revision history
Table 13.
Date Jul-1999 31-Aug-2000 20-Mar-2002 29-May-2002 28-Mar-2003 02-Jul-2003 18-Feb-2005 02-Aug-2010
Document revision history
Revision 1 2 3 3.1 3.2 3.3 4 5 First issue From preliminary data to datasheet Reformatted; temperature information added to tables (Table 7, 8, 3, 4, 9, 10) Modified "VCC noise and negative going transients" text Remove 5 V/5%, add 3 V part (Figure 1, 2, 9; Table 5, 6, 8, 2, 3, 4, 9, 10, 12) Changed characteristic (Table 8) Reformatted; IR reflow update (Table 5) Updated Features, Section 3, Table 12; added ECOPACK(R) text to Section 5; added Section 7: Environmental information. Changes
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M48Z2M1Y, M48Z2M1V
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